This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-287717, filed Sep. 21, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device having a ground plane and a manufacturing method thereof. More specifically, the present invention concerns a ground plane and a formation method thereof applied to semiconductor elements such as logic LSI (Large Scale Integrated circuit), memory LSI including DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), and analog LSI comprising bipolar transistors.
2. Description of the Related Art
Generally, the multilayer wiring used for semiconductor elements is easily affected by a signal noise (crosstalk noise) due to mutual capacitance or mutual inductance between adjacent connections. In recent years, as interconnections become finer, the affect of this crosstalk noise increases and is becoming a cause of preventing fabrication of high-speed elements. Particularly in the field of LSI evaluation boards, crosstalk noise is becoming hindrance to evaluation of LSI""s high performance.
An LSI evaluation board having damascene structure plate electrodes is proposed as a solution for decreasing the crosstalk noise. This board is provided with a metallic plate having ground potentials called a ground plane at least on or under the wiring.
There is an increasing demand for applying such a structure for decreasing the crosstalk noise in ordinary LSI chips.
FIGS. 9A and 9B provide examples of applying a ground plane used for conventional LSI evaluation boards to ordinary LSI chips.
In FIG. 9A, an insulator 102 is formed on an Si substrate 101. On the surface of the insulator 102, there are formed damascene-structure lower layer wirings 103A and 103B. The lower layer wirings 103A and 103B are made of liner metal 103a such as TaN and wiring metal 103b such as Cu, respectively.
An interlayer film 105 is formed via a barrier film 104 on the insulator 102 provided with the lower layer wirings 103A and 103B. On the interlayer film 105, there are formed dual damascene structure connection wirings 106A and 106B. The connection wiring 106A leads to the lower layer wiring 103A. The connection wiring 106B leads to the lower layer wiring 103B. The connection wiring 106A comprises a ViaPlug section 106A-1 and a wiring section 106A-2. The connection wiring 106B comprises a ViaPlug section 106B-1 and a ground plane 106B-2. The connection wiring 106A and 106B are made of liner metal 106a such as TaN and plug metal 106a such as Cu, respectively.
An interlayer film 108 is formed via a barrier film 107 on the interlayer film 105 provided with the connection wirings 106A and 106B. On the interlayer film 108, there is formed a dual damascene structure upper layer wiring 109 leading to the connection wiring 106A. The upper layer wiring 109 comprises a ViaPlug section 109A-1 and a wiring section 109A-2. The upper layer wiring 109 is formed of liner metal 109a such as TaN and wiring metal 109b such as Cu.
In this configuration, a ground potential is supplied to the ground plane 106B-2 via the lower layer wiring 103B. This suppresses occurrence of crosstalk noise due to mutual capacitance or mutual inductance between adjacent wirings.
However, there arise various problems when a conventional multilayer wiring process is used to provide the above-mentioned configuration. For example, when the ground plane 106B-2 is formed by a formation process for dual damascene wiring which is being put to practical use, say, for Cu wiring, a phenomenon called xe2x80x9cdishingxe2x80x9d occurs. In this case, as shown in FIG. 9B, there is the problem that the inside of a pattern sinks largely. For example, when the CMP (Chemical Mechanical Polishing) method is used to flatten Cu, dishing occurs, which excessively scrapes the inside of a wide pattern such as the ground plane 106B-2. This phenomenon is not only an obstacle to the ground potential, but also may adversely affect lithography and CMP when wiring is formed on a layer thereon.
As mentioned above, a prior art method can decrease crosstalk noise by forming the ground plane. This, however, has the drawback that dishing causes the inside of a pattern to sink largely when an attempt is made to provide the ground plane by means of a conventional formation process for dual damascene wiring.
According to a first aspect of the present invention, there is provided a semiconductor device comprising at least first and second lower layer wirings provided on a surface of an insulator on a semiconductor substrate; a first interlayer film provided on the insulator to cover surfaces of the first and second lower layer wirings; first and second connection wirings which are provided on the first interlayer film and comprise first and second films contacting the first and second lower layer wirings respectively; and a plate electrode which is continuously provided on the second connection wiring and comprise the first film.
According to a second aspect of the present invention, there is provided a manufacturing method of a semiconductor device comprising forming at least first and second lower layer wirings on a surface of an insulator provided on a semiconductor substrate; forming a first interlayer film on the insulator to cover surfaces of the first and second lower layer wirings; forming first and second through-holes which reach the first and second lower layer wirings through the first interlayer film; forming a first film on a surface of the first interlayer film including insides of the first and second through-holes; forming a second film on the first film and completely filling the first and second through-holes; selectively removing the second film remaining on the first film except insides of the first and second through-holes; and patterning the first film and forming first and second connection wirings connected to the first and second lower layer wirings respectively and a plate electrode continuous with the second connection wiring.